Low-Power Two-Phase Clock Generator Architectures for CMOS Circuits

Low-Power Two-Phase Clock Generator Architectures for CMOS Circuits

Introduction

Two-phase clock generators produce two non-overlapping clock signals (φ1, φ2) used widely in dynamic logic, charge-coupled devices, and clocked storage elements. Low-power design is critical for battery-powered and energy-constrained CMOS systems. This article explains low-power objectives, common architectures, key design techniques, and practical trade-offs for implementing efficient two-phase clock generators.

Low-power design objectives

• Minimize dynamic switching: Reduce capacitor charging/discharging energy and switching frequency where possible.
• Reduce leakage: Use transistor sizing, stacking, and power-gating to limit subthreshold and gate leakage.
• Maintain timing integrity: Ensure non-overlap, duty-cycle control, and low jitter while conserving energy.
• Area and complexity: Favor compact implementations with few analog components when integration cost matters.

Basic architecture categories

1. Ring-oscillator-based generators
2. PLL/DLL-based solutions
3. Delay-line/edge-shaping circuits
4. Charge-pump / bootstrapped switches for low-loss transmission

1. Ring-oscillator-based generators

• Structure: Odd-numbered inverter chain (ring oscillator) followed by logic to derive two phases.
• Strengths: Simple, fully digital, easy to integrate, low area.
• Low-power techniques:
  • Use fewer stages and low-supply-voltage design to reduce switching energy.
  • Implement current-starving or digitally-controlled delay elements to slow oscillation when full speed isn’t needed.
  • Power-gate sections during idle periods.
• Trade-offs: Higher phase noise/jitter versus PLLs; frequency control coarse without additional control loops.

2. PLL/DLL-based solutions

• Structure: Phase-locked loop (PLL) or delay-locked loop (DLL) generates precise frequency and phase; two phases derived from quadrature or controlled divider/phase interpolator.
• Strengths: Tight frequency/phase control, low jitter, stable duty cycle.
• Low-power techniques:
  • Use DLL instead of PLL for lower power when only phase alignment is required.
  • Use low-power phase detectors (e.g., bang-bang or sampled-data detectors) and simplified loop filters.
  • Employ duty-cycled or adaptive biasing for VCO/VCDL to reduce static current when not locked or at lower speeds.
  • Use coarse/fine control: coarse digital divider for large adjustments, fine voltage control only when necessary.
• Trade-offs: Higher complexity and area; analog components may dominate power if not carefully optimized.

3. Delay-line and edge-shaping circuits

• Structure: A single high-quality clock edge is split and passed through matched delay cells; complementary phases formed and non-overlap enforced via logic gates.
• Strengths: Moderate complexity, good control of non-overlap, avoids continuous oscillator power draw.
• Low-power techniques:
  • Use sparse or event-driven delay tuning: enable delay elements only when switching or during calibration.
  • Implement gate-level logic with minimum drive strength sufficient for downstream loads.
  • Exploit local resonant or adiabatic techniques for very low-energy charge transfer (specialized).
• Trade-offs: Delay element accuracy and matching affect phase timing; calibration may be needed over PVT.

4. Charge-pump and bootstrapped switch techniques

• Purpose: Reduce energy loss during switch transitions, critical when using transmission gates or pass transistors for clock distribution.
• Techniques:
  • Bootstrapped transmission gates hold near-constant gate-source voltage to reduce on-resistance and switching energy.
  • Charge-pump circuits recycle charge between phases instead of dissipating it to rails.
  • Implement adiabatic switching where feasible to approach reversible logic energy savings.
• Trade-offs: Added circuit complexity and control; may require careful sizing and layout to avoid reliability issues.

Key practical design techniques

• Clock gating and adaptive frequency scaling: Gate clocks to inactive regions and lower frequency or voltage when workload permits.
• Non-overlap tuning: Use digitally adjustable delays or feedback to set minimum necessary non-overlap, minimizing dead time while preventing short-circuit currents.
• Duty-cycle and phase balancing: Use symmetric layout, matched loadings, and balanced routing to preserve amplitude and timing.
• Low-voltage operation: Design transistors and logic to operate at reduced VDD; consider body-biasing to control thresholds.
• Transistor sizing: Optimize for capacitive loading — smaller devices reduce dynamic power but increase delay; size drivers for minimum energy per transition.
• Calibration and PVT compensation: Digital calibration loops or background tuning to maintain timing across process, voltage, temperature variations.
• Spatial clock distribution: Local generation of two-phase clocks near the load reduces distribution capacitance and energy.

Design examples (concise)

• Low-power ring-based: 3-stage ring with current-starved inverters + edge-extractor producing φ1/φ2 with programmable delay elements. Use power gating when idle.
• DLL-based generator: Reference clock -> VCDL with digitally controlled taps -> phase-select logic produces φ1/φ2; VCDL bias is adaptive based on required frequency.
• Charge-recycle splitter: Single clock drives capacitor network that redistributes charge to form complementary phases, reducing net energy drawn from supply.

Trade-offs summary

• Simplicity vs. precision: Ring oscillators are simple/compact but noisy; PLL/DLL are precise but cost more power/area.
• Continuous vs. event-driven power: Continuous oscillators consume standby power; event-driven or on-demand generators save energy when idle.
• Non-overlap length: Longer non-overlap prevents short circuits but increases inactive time for dynamic nodes, potentially increasing refresh energy.

Layout and implementation tips

• Place two-phase generator close to the load to reduce routing capacitance.
• Match rising/falling path parasitics to maintain phase symmetry.
• Shield sensitive analog blocks and use separate well ties where needed to minimize substrate noise.
• Simulate across corners and include Monte Carlo for mismatch sensitivity of non-overlap and phase jitter.

Conclusion

Selecting a low-power two-phase clock generator requires balancing precision, area, and energy. For ultra-low-power or bursty workloads, event-driven ring or delay-based generators with aggressive clock gating and charge-recycle techniques excel. For applications demanding tight timing and low jitter, a carefully optimized DLL with adaptive biasing is preferable. Combining techniques—local generation, charge recycling, and calibration—typically yields the best energy efficiency for CMOS two-phase clock generation.